Altium

Design Rule Verification Report

Date: 11/03/2026
Time: 4:37:14 PM
Elapsed Time: 00:00:00
Filename: C:\Users\jack.spencer\AppData\Local\Temp\Releases\Snapshot\2\RD09.PcbDoc
Warnings: 0
Rule Violations: 0
Waived Violations: 15
PCB Health Issues: 4

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=11.811mil) (InNetClass('RF-Net') and ( IsArc or IsTrack )),((InPolygon)) 0
Clearance Constraint (Gap=6mil) (OnLayer('Keep-Out Layer')),((InPolygon)) 0
Clearance Constraint (Gap=7mil) ((IsVia AND InNetClass('RF-Net'))),(All) 0
Clearance Constraint (Gap=5mil) (Not(OnLayer('Keep-Out Layer'))),(Not(OnLayer('Keep-Out Layer'))) 0
Clearance Constraint (Gap=4mil) ((InPolygon)),(All) 0
Clearance Constraint (Gap=5.744mil) (InNet('USB_D_N') or InNet('USB_D_P')),((InPolygon)) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=3.945mil) (Max=20mil) (Preferred=19.846mil) ((InNetClass('RF-Net'))) 0
Width Constraint (Min=5mil) (Max=100mil) (Preferred=8mil) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=19.685mil) (Conductor Width=7.874mil) (Air Gap=7.874mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=2.52mil) (All) 0
Hole Size Constraint (Min=5.906mil) (Max=100mil) (Disabled)(All) 0
Hole To Hole Clearance (Gap=8mil) (All),(All) 0
Silk To Solder Mask (Clearance=7.7mil) (IsPad),(All) 0
Silk to Silk (Clearance=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (All) 0
Component Clearance Constraint ( Horizontal Gap = 39.37mil, Vertical Gap = 3.937mil ) (InComponentClass('COMP_BGA')),(InComponentClass('COMP_BGA')) 0
Component Clearance Constraint ( Horizontal Gap = 11.811mil, Vertical Gap = 3.937mil ) (InComponentClass('CHIP_MICRO')),(InComponentClass('COMP_BGA')) 0
Component Clearance Constraint ( Horizontal Gap = 23.622mil, Vertical Gap = 3.937mil ) (InComponentClass('COMP_BGA')),(InComponentClass('COMP_OTHER')) 0
Component Clearance Constraint ( Horizontal Gap = 14.961mil, Vertical Gap = 3.937mil ) (InComponentClass('COMP_OTHER')),(InComponentClass('COMP_OTHER')) 0
Component Clearance Constraint ( Horizontal Gap = 11.811mil, Vertical Gap = 3.937mil ) (InComponentClass('CHIP_MICRO')),(InComponentClass('COMP_OTHER')) 0
Component Clearance Constraint ( Horizontal Gap = 14.961mil, Vertical Gap = 3.937mil ) (InComponentClass('CHIP_OTHER')),(InComponentClass('COMP_OTHER')) 0
Component Clearance Constraint ( Horizontal Gap = 7.874mil, Vertical Gap = 3.937mil ) (InComponentClass('CHIP_MICRO')),(InComponentClass('CHIP_MICRO')) 0
Component Clearance Constraint ( Horizontal Gap = 11.811mil, Vertical Gap = 10mil ) (InComponent('SHIELD')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 9.842mil, Vertical Gap = 3.937mil ) (InComponentClass('CHIP_MICRO')),(InComponentClass('CHIP_OTHER')) 0
Component Clearance Constraint ( Horizontal Gap = 14.961mil, Vertical Gap = 3.937mil ) (InComponentClass('CHIP_OTHER')),(InComponentClass('COMP_BGA')) 0
Component Clearance Constraint ( Horizontal Gap = 9.842mil, Vertical Gap = 3.937mil ) (InComponentClass('CHIP_OTHER')),(InComponentClass('CHIP_OTHER')) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 0

Waived Violations Count
Clearance Constraint (Gap=5mil) (Not(OnLayer('Keep-Out Layer'))),(Not(OnLayer('Keep-Out Layer'))) 5
Board Clearance Constraint (Gap=0mil) (All) 10
Total 15

PCB Health Issues Count
Invalid PCB Design Rules 1
Reference Point Outside the Component Area 3
Total 4

Rule Violations

Waived Violations

Clearance Constraint (Gap=5mil) (Not(OnLayer('Keep-Out Layer'))),(Not(OnLayer('Keep-Out Layer')))
Clearance Constraint: (4.724mil < 5mil) Between Pad U2-1(820.814mil,68.803mil) on Bottom Layer And Region (0 hole(s)) Bottom Layer
Waived by Matthew Jay at 3/04/2025 3:42:37 PM
Accept
Clearance Constraint: (4.724mil < 5mil) Between Pad U2-2(846.404mil,68.803mil) on Bottom Layer And Region (0 hole(s)) Bottom Layer
Waived by Matthew Jay at 3/04/2025 3:42:37 PM
Accept
Clearance Constraint: (4.724mil < 5mil) Between Pad U2-3(871.995mil,68.803mil) on Bottom Layer And Region (0 hole(s)) Bottom Layer
Waived by Matthew Jay at 3/04/2025 3:42:37 PM
Accept
Clearance Constraint: (4.724mil < 5mil) Between Pad U2-4(871.995mil,-0.095mil) on Bottom Layer And Region (0 hole(s)) Bottom Layer
Waived by Matthew Jay at 3/04/2025 3:42:37 PM
Accept
Clearance Constraint: (4.724mil < 5mil) Between Pad U2-6(820.814mil,-0.095mil) on Bottom Layer And Region (0 hole(s)) Bottom Layer
Waived by Matthew Jay at 3/04/2025 3:42:37 PM
Accept
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Board Clearance Constraint (Gap=0mil) (All)
Board Outline Clearance(Outline Edge): (5.795mil < 6mil) Between Board Edge And Pad H1-1(60.165mil,-10.827mil) on Top Layer
Waived by Brian Attride at 24/12/2025 9:10:46 AM
Board clearance OK. It's the same as the previous build
Board Outline Clearance(Outline Edge): (2.795mil < 6mil) Between Board Edge And Pad H1-2(110.165mil,-10.826mil) on Bottom Layer
Waived by Brian Attride at 24/12/2025 9:10:46 AM
Board clearance OK. It's the same as the previous build
Board Outline Clearance(Outline Edge): (2.795mil < 6mil) Between Board Edge And Pad H1-2(145.165mil,-100.826mil) on Top Layer
Waived by Brian Attride at 24/12/2025 9:10:46 AM
Board clearance OK. It's the same as the previous build
Board Outline Clearance(Outline Edge): (2.796mil < 6mil) Between Board Edge And Pad H1-2(145.165mil,79.174mil) on Top Layer
Waived by Brian Attride at 24/12/2025 9:10:46 AM
Board clearance OK. It's the same as the previous build
Board Outline Clearance(Outline Edge): (Collision < 6mil) Between Board Edge And Text ".Layer_Name" (352.306mil,-359.75mil) on Bottom Overlay
Waived by Brian Attride at 25/07/2025 11:54:27 AM
Label used to display layer in fabriaction document
Board Outline Clearance(Outline Edge): (Collision < 6mil) Between Board Edge And Text ".Layer_Name" (377.038mil,-359.75mil) on Bottom Layer
Waived by Brian Attride at 25/07/2025 11:54:27 AM
Label used to display layer in fabriaction document
Board Outline Clearance(Outline Edge): (Collision < 6mil) Between Board Edge And Text ".Layer_Name" (389.75mil,-359.75mil) on Top Overlay
Waived by Brian Attride at 25/07/2025 11:54:27 AM
Label used to display layer in fabriaction document
Board Outline Clearance(Outline Edge): (Collision < 6mil) Between Board Edge And Text ".Layer_Name" (413.188mil,-359.75mil) on Mid Layer 2
Waived by Brian Attride at 25/07/2025 11:54:27 AM
Label used to display layer in fabriaction document
Board Outline Clearance(Outline Edge): (Collision < 6mil) Between Board Edge And Text ".Layer_Name" (414.481mil,-359.75mil) on Top Layer
Waived by Brian Attride at 25/07/2025 11:54:27 AM
Label used to display layer in fabriaction document
Board Outline Clearance(Outline Edge): (Collision < 6mil) Between Board Edge And Text ".Layer_Name" (416.694mil,-359.75mil) on Mid Layer 1
Waived by Brian Attride at 25/07/2025 11:54:27 AM
Label used to display layer in fabriaction document
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PCB Health Issues

Invalid PCB Design Rules
Invalid PCB Design Rules: RoutingVias
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Reference Point Outside the Component Area
Reference point outside the component area: SMT Small Component TP8-PAD0035 (1408.395mil,-206.929mil) on Bottom Layer
Reference point outside the component area: SMT Small Component TP7-PAD0035 (1178.068mil,-206.929mil) on Bottom Layer
Reference point outside the component area: SMT Small Component TP4-PAD0035 (392.716mil,118.11mil) on Bottom Layer
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