Design Rule Verification Report

Date:		21/10/2024
Time:		9:13:08 AM
Elapsed Time:		00:00:01
Filename:		C:\Users\Brian Attride\AppData\Local\Temp\Releases\Snapshot\2\MMECH06.PcbDoc

Warnings:		0
Rule Violations:		0
Waived Violations:		3

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0.152mm) (All),(All)	0
Clearance Constraint (Gap=0mm) (InComponent('FID1')),(All)	0
Clearance Constraint (Gap=0.255mm) ((InPolygon)),(InNetClass('RF-Net'))	0
Clearance Constraint (Gap=0mm) (InComponent('FID2')),(All)	0
Clearance Constraint (Gap=0mm) (InComponent('FID3')),(All)	0
Clearance Constraint (Gap=0.254mm) (InNetClass('RF-Net')),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Un-Connected Pin Constraint ( (Disabled)(All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=0.178mm) (Max=1mm) (Preferred=0.254mm) (InNetClass('RF-Net'))	0
Width Constraint (Min=0.203mm) (Max=1.27mm) (Preferred=0.203mm) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=0.4mm) (Conductor Width=0.254mm) (Air Gap=0.2mm) (Entries=4) ((InComponent('J5') OR InComponent('J6') OR InComponent('J13') OR InComponent('J11') OR InComponent('J12')))	0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)	0
Hole Size Constraint (Min=0.203mm) (Max=5.08mm) (All)	0
Hole To Hole Clearance (Gap=0.203mm) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0.076mm) (not InComponent('U4','U1','U5','U6','U7','U8','U9','U10','H2','H3')),(All)	0
Silk To Solder Mask (Clearance=0.102mm) (Disabled)(IsPad),(All)	0
Silk to Silk (Clearance=0.203mm) (Disabled)(All),(All)	0
Net Antennae (Tolerance=0mm) (All)	0
Board Clearance Constraint (Gap=0mm) ((not OnTopSilkscreen) AND (NOT OnBottomSilkscreen) and (not OnMultiLayer))	0
Matched Lengths(Tolerance=1.27mm) (InxSignalClass('xSignals_U1_Passives_J5_MatchLengthsClass_1'))	0
Matched Lengths(Tolerance=1.27mm) (InxSignalClass('xSignals_U1_Passives_J5_MatchLengthsClass'))	0
Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0.254mm ) (Disabled)(All),(All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (Disabled)(All)	0
Height Constraint (Min=0mm) (Max=7mm) (Prefered=5mm) (InComponentClass('POGO'))	0
Height Constraint (Min=0mm) (Max=12mm) (Prefered=3mm) (InComponent('TP1'))	0
Height Constraint (Min=0mm) (Max=4mm) (Prefered=3mm) (WithinRoom('ROOM_SOCKET'))	0
Total	0

Waived Violations	Count
Board Clearance Constraint (Gap=0mm) ((not OnTopSilkscreen) AND (NOT OnBottomSilkscreen) and (not OnMultiLayer))	3
Total	3

Rule Violations

Waived Violations

Board Clearance Constraint (Gap=0mm) ((not OnTopSilkscreen) AND (NOT OnBottomSilkscreen) and (not OnMultiLayer))
Board Outline Clearance(Outline Edge): (Collision < 0.152mm) Between Board Edge And Text ".Layer_Name" (39.7mm,-2.75mm) on Bottom Layer Waived by Brian Attride at 11/06/2024 4:00:30 PM Waived. label outside of board edge. Not an issue
Board Outline Clearance(Outline Edge): (Collision < 0.152mm) Between Board Edge And Text ".Layer_Name" (39.7mm,-2.75mm) on Mid Layer 1 Waived by Brian Attride at 11/06/2024 4:00:30 PM Waived. label outside of board edge. Not an issue
Board Outline Clearance(Outline Edge): (Collision < 0.152mm) Between Board Edge And Text ".Layer_Name" (39.7mm,-2.75mm) on Top Layer Waived by Brian Attride at 11/06/2024 4:00:30 PM Waived. label outside of board edge. Not an issue